-- B. Alex Bridges -- ECE-476, Summer '99 -- Lab #01, Problem #03 ENTITY FullSubtractor IS PORT(x,y,bIn : IN BIT; d,bOut : OUT BIT); END FullSubtractor; ARCHITECTURE logic OF FullSubtractor IS BEGIN main : PROCESS BEGIN bOut <= (NOT x AND (y OR bIn) ) OR (y and bIn); d <= x XOR y XOR bIn; WAIT ON x,y,bIn; END PROCESS main; END logic;