LIBRARY ieee;
use ieee.math_real.all;


ENTITY tester IS
    PORT(go:IN BIT);
END tester;

ARCHITECTURE test OF tester IS 

  COMPONENT affine 
    PORT(x_in,y_in,z_in,
         rotate_x,rotate_y,rotate_z,
         trans_x,trans_y,trans_z,
         scale_x,scale_y,scale_z,scale_factor: IN REAL;
         control: IN BIT_VECTOR(9 downto 0);
         x_out,y_out,z_out:OUT REAL);
  END component;
    SIGNAL x,y,z,rx,ry,rz,tx,ty,tz,sx,sy,sz,sf,x_out,y_out,z_out:REAL := 0.0;
    SIGNAL control : BIT_VECTOR(9 downto 0);
    TYPE tuple_6 IS array(0 to 5) OF REAL;
    TYPE data_matrix IS array(0 to 9) OF tuple_6;

    signal clock:BIT;

BEGIN
    transform: affine port map( x,y,z, rx,ry,rz, tx,ty,tz, sx,sy,sz, sf, control,
                                x_out,y_out,z_out);
    PROCESS (clock)
    BEGIN
        clock <= not clock after 10 ns;
    END PROCESS;

    process
        variable data:data_matrix;
        variable tuple : tuple_6;
    begin
        control <= "0000000000";
        
        
        FOR i IN 0 to 9 LOOP
          for j IN 0 to 2 loop
             data(i)(j) := 1.0;
          end loop;

          x <= data(i)(0);
          y <= data(i)(1);
          z <= data(i)(2);
          
          data(i)(3) := x_out;
          data(i)(4) := y_out;
          data(i)(5) := z_out;

        END loop;
        wait ON clock;
    end PROCESS;    
END tesLIBRARY ieee;